In the field of semiconductor devices, with a trend of miniaturization, various investigations have been made on materials with a low dielectric constant (hereinafter, also referred to as “low-k materials”) that have a porous structure, as an interlayer dielectric layer of a semiconductor.
In a semiconductor interlayer dielectric layer having a porous structure, when the void fraction thereof is increased in order to further lower the dielectric constant, a metal component such as copper, which is embedded as a wiring material, may readily enter the fine pores of the semiconductor interlayer dielectric layer, thereby increasing the dielectric constant or generating a leak current.
On the other hand, in the semiconductor device production method by using a porous, low dielectric constant material, a technique of sealing fine pores on side walls of grooves that have been formed by etching, using a micelle-type surfactant in wet washing after the etching, has been known (see, for example, Patent Document 1).
Further, when the low-k material has a hydrophobic surface, a technique of controlling the hydrophilicity or hydrophobicity of the material by applying a polyvinyl alcohol-based amphipathic polymer to its surface has been known (see, for example, Patent Document 2).
Moreover, a composition for polishing a semiconductor, which includes a cationic polymer and a surfactant, has been known (see, for example, Patent Document 3).
In the method for manufacturing a semiconductor device by using a porous, low dielectric constant material, at the time of sealing fine pores on side walls or the like of grooves that have been formed by etching, if there is a wiring line formed from copper or the like on the surface of the substrate together with a porous interlayer dielectric layer, the material used for sealing (sealing composition) may adhere to the wiring line. Such an extra sealing composition needs to be removed, since it may cause circuit malfunction or corrosion of a semiconductor device. As such, there has been a demand for a method (hereinafter, also referred to as a “rinsing method”) of rapidly removing the extra sealing composition on the wiring line, while leaving the material that seals the fine pores, and a rinse (hereinafter, also referred to as a “cleaning agent”).
Further, an extra material that does not form a constituent element of a semiconductor circuit, which exists on the peripheral area of the surface of a semiconductor substrate on which a circuit is not formed or at the back face of the semiconductor substrate on which the dielectric film is not formed, and the like, may exfoliate during the process of manufacturing the semiconductor, and may contaminate the semiconductor substrate. Therefore, the extra material needs to be removed by a method such as back rinsing or edge rinsing. Accordingly, there has been a demand for a method of rapidly removing the film that is formed on a semiconductor device.    [Patent Document 1] Japanese National Phase Publication No. 2009-503879    [Patent Document 2] WO 09/012184, Pamphlet    [Patent Document 3] Japanese Patent Application Laid-Open (JP-A) No. 2006-352042